1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method for controlling the semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit in which a memory self-test circuit and a redundancy repair analyzing circuit are built and to a method for controlling the semiconductor integrated circuit.
2. Related Art
A method is known by building a built-in self-test circuit (hereinafter, referred to as a ‘BIST circuit’) in a built-in memory of a semiconductor integrated circuit, in which an error is detected from the memory in a manufacturing test. Examples of the BIST circuit are a comparator-type BIST circuit that compares written data with read data to determine whether an error occurs and a compactor-type BIST circuit that compacts a read result and determines whether an error occurs based on the compacted result.
In addition, a redundancy repair technique in which an embedded memory that is determined as a defective memory is repaired using memory cells having a redundancy structure is known. The memory cells having the redundancy structure includes a row spare or a column spare. In the simplest structure, memory cells include a set of row spares or column spares for each repair unit. In more complicated structure, any of the following structures is a structure in which memory cells include both a row spare and a column spare, a structure in which memory cells include a plurality of row spares or column spares, and a structure in which one memory array is divided into a plurality of segments and memory cells having a repair structure is provided in each segment.
In order to use the redundancy repair technique for the manufacture of a semiconductor integrated circuit and a memory test, it is necessary to perform analysis using the result of the memory test, determine the error position of a memory and a spare used for repair (hereinafter, referred to as a ‘repair analysis result’), and perform redundancy allocation based on the determined repair analysis result. In general, a direct access circuit that directly accesses a memory and a memory tester are used to perform the memory test, the fail bit map of the output of the memory is written into a storage unit of the memory tester, and a program in the memory tester starts to perform analysis.
However, in a conventional redundancy repair technique, a memory tester having a sufficient storage capacity to store the error information of all bits of a memory is required. Therefore, it is necessary to use both a memory tester and a logic tester to test a memory of a system LSI (Large Scale Integration) including a logic circuit and the memory.
Since a general large scale system LSI includes a large number of embedded memories, it is difficult to prepare the direct access circuit for each memory to be repaired.
As a technique for solving the above-mentioned problems, a built-in redundancy allocation (hereinafter, referred to as ‘BIRA’) circuit which performs analysis and redundancy allocation on a chip is known. The BIRA circuit is used together with the BIST circuit. The BIRA circuit analyzes the error information of a memory based on the error detection result of the BIST circuit to determine a repair analysis result, and outputs the determined repair analysis result as the analysis result. In a manufacturing process, a fuse device for storing the analysis result is programmed by using, for example, a laser blower, to repair a chip. In addition, when the repair analysis result is not determined, the BIRA circuit outputs information indicating that the repair analysis result has not been determined as the analysis result. In this case, the chip is treated as a defective chip. The BIRA circuit can be implemented by a relative small logic circuit, for the minimum redundancy structure having only one set of column spares.
The BIRA circuit determines whether an error occurs in a memory based on data read from the memory while testing, and analyzes the repair analysis result based on information, such as the bit position and address of the memory. In addition, the BIRA circuit updates the repair analysis result, considering the previous result, whenever data is sequentially read from the memory. Since the number of row spares or column spares is limited, it may be difficult to determine the repair analysis results for all errors according to the number of errors or the way of appearance thereof. Therefore, in this case, the BIRA circuit determines that the repair of the memory is unavailable, and outputs information indicating that the repair of the memory is unavailable.
In the both cases, error information for each address and each bit is required to analyze the repair analysis result. The BIST circuit using an output comparator compares the output of a memory with an expected output value by each bit and determines whether an error occurs based on the comparison result. The BIRA circuit can also use error information for each bit. Therefore, it is possible to prevent, to same extent, an increase in the number of circuits for each memory instance due to the addition of the function of the BIRA circuit.
However, even when error information for each bit is input, the BIRA circuit needs to determine whether repair is available based on the information, and generate a repair analysis result when it is determined that repair is available. This operation is generally performed by an encoder logic circuit. However, when the bit width of a memory is large, the size of a combination of the encoder logic circuit and the BIRA circuit is increased. In particular, the BIRA circuit is provided for each memory instance. Therefore, as the number of memory instances to be repaired is increased, the number of BIRA circuits in the entire semiconductor integrated circuit is increased. The BIRA circuits occupy a large portion of the logic circuit in the semiconductor integrated circuit.
In contrast, the following techniques are known. One technique in which one BIST circuit is provided for a plurality of memories, and the BIST circuit sequentially tests the memories, analyzes the repair analysis result thereof, and generates the analyzed repair analysis result (see Japanese Patent Laid-Open Publication No. 2002-319298) is known. Another technique in which the analysis of a repair analysis result and the output of the repair analysis result are sequentially performed (see Japanese Patent Laid-Open Publication 8-255500) is known.
However, in the above-mentioned techniques, the BIST circuit needs to stop whenever each memory is tested. Therefore, it is difficult to perform the next test until the analysis of a defective memory and the generation of a repair analysis result corresponding to the test are completely performed. As a result, the time required to test a memory is increased.